Manufacturers of highly complex circuit designs, such as Central Processing Units (CPU's), typically require verification of design in order to verify that the circuits are designed properly. One common method of design verification is ad hoc verification. Ad hoc verification allows two different implementations of a design to be compared. Equivalence checkers use mathematical methods to formally compare a first version of a design with a second version of the design, checking that logic functions in the first version are equivalent to logic functions in the second version. Typically, with ad hoc verification, one of the versions already has been verified, and serves as a specification, or reference, against which the other version is verified.
Ad hoc verification may be implemented using entities shown in FIG. 1. An Instruction Set Simulator (ISS) (10) is typically a computer program (e.g., written in C++) running on a conventional computer. A Hardware Definition Language (HDL) simulator (12) generally runs a program written in an HDL, such as Verilog. Often, the HDL simulator (12) runs on the same conventional computer upon which the ISS runs. Sometimes the HDL simulator (12) is implemented on a hardware accelerator, such as CoBALT™ (a registered trademark of Cadence Design Systems, Inc.). A simulation design (14), i.e., a circuit design, is used to create an ISS simulation (16) and an HDL simulation (18). Both the ISS (10) and the HDL simulator (12) send results to a comparator (20), and output of the comparator (20) is sent to a diagnostic output device (22).
Ad hoc verification using entities shown in FIG. 1 may be implemented as shown in a flow diagram in FIG. 2. First, a simulation design is generated (Step 50). The simulation design may be written in an HDL, such as Verilog. Then, the ISS simulation and the HDL simulation are generated using the simulation design (Step 52). Once generated, the ISS simulation and the HDL simulation are input into the ISS and the HDL simulator (Step 54), and a current cycle of both of the ISS simulation and of the HDL simulation is executed (Step 56). At the start of both the ISS simulation and the HDL simulation, a first cycle is executed. The ISS simulation and the HDL simulation are synchronized with respect to simulation cycles.
Next, the ISS simulation results and the HDL simulation results for the current cycle are sent from the ISS and the HDL simulator, respectively, to the comparator (Step 58). Because the ISS and the HDL simulator often operate at different speeds, there is often a time lag between output of the ISS and the HDL simulator, especially if the HDL simulator is a hardware accelerator. Thus, an issue of communication bottlenecks caused by different speeds of simulation is often a concern when using ad hoc verification.
Once both the HDL simulator and the ISS simulation results for the current cycle are received by the comparator, the results are compared (Step 60). Comparison of the HDL simulation and the ISS simulation results involve comparing state of the HDL simulation and the ISS simulation. For example, the simulation design may include a particular element (e.g., a gate, an adder, a register, etc.). The output value (i.e., a “1” or a “0”) of the element at each cycle is a portion of the state of the simulation, for both the HDL simulation and the ISS simulation.
A determination is then made as to whether the results of the ISS simulation and the HDL simulation match (Step 62). If the results do match, a determination is made as to whether the simulation has ended (Step 64). If the simulation has not ended, the ISS simulation and the HDL simulation are both advanced to a next cycle (Step 66).
Otherwise, if the results of the ISS simulation and the HDL simulation do not match, the results are labeled a failure (Step 68), and diagnostic output is generated (Step 70). A determination is then made as to whether the simulation has ended (Step 64). If the simulation has not ended, the ISS simulation and the HDL simulation are both advanced to a next cycle (Step 66), and both simulations continue until both simulations end.
Although cycle-by-cycle verification as shown in FIG. 2 is appropriate for certain verification implementations, in other verification implementations, execution of the simulation design may be required to run for multiple cycles before comparison between the HDL simulation and the ISS simulation. For example, the HDL simulation and the ISS simulation may run for 10,000 cycles, and then state values of the HDL simulation and the ISS simulation are compared.
For verification implementations that use multiple cycle runs, e.g., 10,000 cycles, designers of circuit verification systems may address certain error detection issues that may arise. For example, if a simulation runs 10,000 cycles, a possibility arises that a first error may occur at a particular cycle, e.g., cycle 1000. The first error causes an improper state value for a particular element. For example, an adder may have an improper state of “1” at the end of cycle 1000, where a proper state is “0”. As the simulation progresses, a second error may occur at cycle 2000. The second error may occur so as to erase the effect of the first error. Thus, after 10,000 simulation cycles, a comparison of the state of the simulation with the state of a reference simulation may show that no error ever occurred, because the second error erased the effect of the first error.